Datasheet

163
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
(1) The filter width is 6 VCLK3 cycles.
7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexer. This multiplexer is defined in Table 7-3. As shown in Figure 7-6 , the output of this selection
multiplexer is inverted and connected to the TZ4n trip-zone input of all ePWMx modules. This connection
allows the application to define the response of each ePWMx module on a phase error indicated by the
eQEP modules.
7.3.3 Input Connection to eQEPx Modules
The input connection to each of the eQEP modules can be selected between a double-VCLK3-
synchronized input or a double-VCLK3-synchronized and filtered input, as listed in Table 7-12.
Table 7-12. Device-Level Input Connection to eQEPx Modules
INPUT SIGNAL
CONTROL FOR DOUBLE-SYNCHRONIZED
CONNECTION TO eQEPx
CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION
(1)
TO eQEPx
eQEP1A PINMMR170[18:16] = 001 PINMMR170[18:16] = 010
eQEP1B PINMMR170[26:24] = 001 PINMMR170[26:24] = 010
eQEP1I PINMMR171[2:0] = 001 PINMMR171[2:0] = 010
eQEP1S PINMMR171[10:8] = 001 PINMMR171[10:8] = 010
eQEP2A PINMMR171[18:16] = 001 PINMMR171[18:16] = 010
eQEP2B PINMMR171[26:24] = 001 PINMMR171[26:24] = 010
eQEP2I PINMMR172[2:0] = 001 PINMMR172[2:0] = 010
eQEP2S PINMMR172[10:8] = 001 PINMMR172[10:8] = 010
(1) The filter width is 6 VCLK3 cycles.
7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
Table 7-13. eQEPx Timing Requirements
(1)
TEST CONDITIONS MIN MAX UNIT
t
w(QEPP)
QEP input period
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
t
w(INDEXH)
QEP Index Input High Time
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
t
w(INDEXL)
QEP Index Input Low Time
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
t
w(STROBH)
QEP Strobe Input High Time
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
t
w(STROBL)
QEP Strobe Input Low Time
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
Table 7-14. eQEPx Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(CNTR)xin
Delay time, external clock to counter increment 4 t
c(VCLK3)
cycles
t
d(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output 6 t
c(VCLK3)
cycles