Datasheet

www.ti.com SCI/LIN Control Registers
Table 28-16. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued)
Bit Field Value Description
26 SET FE INT Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN module to generate an interrupt when a framing error occurs.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
25 SET OE INT Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN module to generate an interrupt when an overrun error occurs.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
24 SET PE INT Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables
the SCI/LIN module to generate an interrupt when a parity error occurs.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
23-19 Reserved 0 Read returns 0. Writes have no effect.
18 SET RX DMA ALL Set receive DMA all. This bit is effective in SCI-compatible mode only. This bit determines if a
separate interrupt is generated for the address frames sent in multiprocessor communications.
When this bit is 0, RX interrupt requests are generated for address frames and DMA requests
are generated for data frames. When this bit is 1, RX DMA requests are generated for both
address and data frames.
0 Read: The DMA request is disabled for address frames (the receive interrupt request is enabled
for address frames).
Write: No effect.
1 Read and write: The DMA request is enabled for address and data frames.
17 SET RX DMA Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable receiver DMA
requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit
SCISETINT.
0 Read: The DMA request is disabled.
Write: No effect.
1 Read and write: The DMA request is enabled for address and data frames.
16 SET TX DMA Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests
for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated
depending on SET TX INT bit (SCISETINT).
0 Read: Transmit DMA request is disabled.
Write: No effect.
1 Read and write: Transmit DMA request is enabled.
15-14 Reserved 0 Read returns 0. Writes have no effect.
13 SET ID INT Set identification interrupt. This bit is effective in LIN mode only. This bit is set to enable an
interrupt when a valid matching identifier is received. See Section 28.3.1.9 for more details.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
12-10 Reserved 0 Read returns 0. Writes have no effect.
9 SET RX INT Receiver interrupt enable. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN to generate a receive interrupt after a frame has been completely received
and the data is being transferred from SCIRXSHF to SCIRD.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
1397
SPNU562–May 2014 Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
Module
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