Datasheet

EQEPxA or EQEPxB
(x = 1 or 2)
eQEPx
double
sync
(x = 1 or 2)
6 VCLK3
Cycles Filter
EQEP1A
VIM
EQEP1INTn
EQEP1
Module
IO
Mux
EQEP1ENCLK
EQEP1IO
EQEP1I
VBus32
VCLK3
SYS_nRST
EQEP1B
EQEP1IOE
EQEP1SO
EQEP1S
EQEP1SOE
EQEP1ERR
EPWM1/../7
TZ4n
EQEP2A
VIM
EQEP2INTn
EQEP2
Module
EQEP2ENCLK
EQEP2IO
EQEP2I
VBus32
VCLK3
SYS_nRST
EQEP2B
EQEP2IOE
EQEP2SO
EQEP2S
EQEP2SOE
EQEP2ERR
Connection
Selection
Mux
see Note A
see Note A
162
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: RM57L843
Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
7.3 Enhanced Quadrature Encoder (eQEP)
Figure 7-6 shows the eQEP module interconnections on the device.
A. For more detail on the eQEPx input synchronization selection, see Figure 7-7.
Figure 7-6. eQEP Module Interconnections
Figure 7-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double synchronous + filter width) for eQEPx.
Figure 7-7. eQEPx Input Synchronization Selection Detail
7.3.1 Clock Enable Control for eQEPx Modules
Each of the EQEPx modules has a clock enable (EQEPxENCLK) which is controlled by its respective
Peripheral Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the
peripherals, the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register
in the system module. In addition, the peripherals must be released from their power down state by
clearing the respective bit in the PSPWRDWNCLRx register. By default after reset, the peripherals are in
power down state.
Table 7-11. eQEPx Clock Enable Control
eQEP MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
eQEP1 PSPWRDWNCLR3[5] 1
eQEP2 PSPWRDWNCLR3[6] 1