Datasheet
SCI/LIN Control Registers
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28.7 SCI/LIN Control Registers
The SCI/LIN module registers are based on the SCI registers, with added functionality registers enabled
by the LIN MODE bit in the SCIGCR1 register.
These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI/LIN is controlled and
accessed through the registers listed in Table 28-10. Among the features that can be programmed are the
LIN protocol mode, communication and timing modes, baud rate value, frame format, DMA requests, and
interrupt configuration. The base address for the control registers is FFF7 E400h for LIN1/SCI1 and
FFF7 E600h for LIN2/SCI2.
Table 28-10. SCI/LIN Control Registers
Offset Acronym Register Description Section
00h SCIGCR0 SCI Global Control Register 0 Section 28.7.1
04h SCIGCR1 SCI Global Control Register 1 Section 28.7.2
08h SCIGCR2 SCI Global Control Register 2 Section 28.7.3
0Ch SCISETINT SCI Set Interrupt Register Section 28.7.4
10h SCICLEARINT SCI Clear Interrupt Register Section 28.7.5
14h SCISETINTLVL SCI Set Interrupt Level Register Section 28.7.6
18h SCICLEARINTLVL SCI Clear Interrupt Level Register Section 28.7.7
1Ch SCIFLR SCI Flags Register Section 28.7.8
20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Section 28.7.9
24h SCIINTVECT1 SCI Interrupt Vector Offset 1 Section 28.7.10
28h SCIFORMAT SCI Format Control Register Section 28.7.11
2Ch BRS Baud Rate Selection Register Section 28.7.12
30h SCIED Receiver Emulation Data Buffer Section 28.7.13.1
34h SCIRD Receiver Data Buffer Section 28.7.13.2
38h SCITD Transmit Data Buffer Section 28.7.13.3
3Ch SCIPIO0 SCI Pin I/O Control Register 0 Section 28.7.14
40h SCIPIO1 SCI Pin I/O Control Register 1 Section 28.7.15
44h SCIPIO2 SCI Pin I/O Control Register 2 Section 28.7.16
48h SCIPIO3 SCI Pin I/O Control Register 3 Section 28.7.17
4Ch SCIPIO4 SCI Pin I/O Control Register 4 Section 28.7.18
50h SCIPIO5 SCI Pin I/O Control Register 5 Section 28.7.19
54h SCIPIO6 SCI Pin I/O Control Register 6 Section 28.7.20
58h SCIPIO7 SCI Pin I/O Control Register 7 Section 28.7.21
5Ch SCIPIO8 SCI Pin I/O Control Register 8 Section 28.7.22
60h LINCOMPARE LIN Compare Register Section 28.7.23
64h LINRD0 LIN Receive Buffer 0 Register Section 28.7.24
68h LINRD1 LIN Receive Buffer 1 Register Section 28.7.25
5Ch LINMASK LIN Mask Register Section 28.7.26
70h LINID LIN Identification Register Section 28.7.27
74h LINTD0 LIN Transmit Buffer 0 Section 28.7.28
78h LINTD1 LIN Transmit Buffer 1 Section 28.7.29
7Ch MBRS Maximum Baud Rate Selection Register Section 28.7.30
90h IODFTCTRL Input/Output Error Enable Register Section 28.7.31
1388
Serial Communication Interface (SCI)/Local Interconnect Network (LIN) SPNU562–May 2014
Module
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