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1591

V C L K

Pb itT

++=

1 6

11 6

VCLK

PbitT

++=

116

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LIN

28.3.1.4.2 Superfractional Divider

The superfractional divider scheme applies to the following modes:

• LIN master mode (synch field + identifier field + response field + checksum field)

• LIN slave mode (response field + checksum field)

28.3.1.4.3 Superfractional Divider In LIN Mode

Building on the 4-bit fractional divider M (BRSR[27:24], the superfractional divider uses an additional 3-bit

modulating value, illustrated in Table 28-7. The sync field (0x55), the identifier field and the response field

can all be seen as 8-bit data bytes flanked by a start bit and a stop bit. The bits with a 1 in the table will

have an additional VCLK period added to their T

bit

Table 28-7. Superfractional Bit Modulation for LIN Master Mode and Slave Mode

(1)

BRS[30:28] Start Bit D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] Stop Bit

0 0 0 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 1 0

2 1 0 0 0 1 0 0 0 1 0

3 1 0 1 0 1 0 0 0 1 0

4 1 0 1 0 1 0 1 0 1 0

5 1 1 1 0 1 0 1 0 1 1

6 1 1 1 0 1 1 1 0 1 1

7 1 1 1 1 1 1 1 0 1 1

(1)

1. In LIN master mode bit modulation applies to synch field + identifier field + response field

2. In LIN slave mode bit modulation applies to identifier field + response field

The baud rate will vary over a LIN data field to average according to the BRSR[30:28] value by a d

fraction of the peripheral internal clock: 0<d<1.

The instantaneous bit time is expressed in terms of T

VCLK

as follows:

For all P other than 0, and all M and d (0 or 1),

(45)

For P = 0 T

bit

= 32T

VCLK

The averaged bit time is expressed in terms of T

VCLK

as follows:

For all P other than 0, and all M and d (0 <d <1),

(46)

For P = 0 T

bit

= 32T

VCLK

With the superfractional divider, a LIN baud rate of 20 kbps is achievable with an internal clock VCLK of

726 kHz. Furthermore, a rate of 400 kbps is achievable with an VCLK of 14.6 MHz.

1367

SPNU562–May 2014 Serial Communication Interface (SCI)/Local Interconnect Network (LIN)

Module

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