Datasheet
F
LINCLK
F
VCLK
16(P +1 +
M )
16
------
-------------------------------------
For all P other than zero=
F
LINCLK
F
VCLK
32
--------------------
For P = 0=
VCLKbit
T
M
PT
÷
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++=
16
116
LIN
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28.3.1.3 Synchronizer
The synchronizer has three major functions in the messaging between master and slave nodes. It
generates the master header data stream, it synchronizes to the LIN bus for responding, and it locally
detects timeouts. A bit rate is programmed using the prescalers in the BRSR register to match the
indicated LIN_speed value in the LIN description file.
The LIN synchronizer will perform the following functions: master header signal generation, slave
detection and synchronization to message header with optional baud rate adjustment, response
transmission timing and timeout control.
The LIN synchronizer is capable of detecting an incoming break and initializing communication at all
times.
28.3.1.4 Baud Rate
The transmission baud rate of any node is configured by the CPU at the beginning; this defines the bit
time T
bit
. The bit time is derived from the fields P and M in the baud rate selection register (BRSR). There
is an additional 3-bit fractional divider value, field U in the BRSR, which further fine-tunes the data field
baud rate.
The ranges for the prescaler values in the BRSR register are:
P = 0, 1, 2, 3, . . . , 2
24
- 1
M = 0, 1, 2, . . . , 15
U = 0, 1, 2, 3, 4, 5, 6, 7
The P, M, and U values in the BRSR register are user programmable. The P and M dividers could be
used for both SCI mode and LIN mode to select a baud rate. The U value is an additional 3-bit value
determining that “a TVCLK“ (with a = 0,1) is added to each T
bit
as explained in Section 28.3.1.4.2. If the
ADAPT bit is set and the LIN slave is in adaptive baud rate mode, then all these divider values are
automatically obtained during header reception when the synchronization field is measured.
The LIN protocol defines baud rate boundaries as follows:
1kHz ≤ F
LINCLK
≤ 20kHz
All transmitted bits are shifted in and out at T
bit
periods.
28.3.1.4.1 Fractional Divider
The M field of the BRSR register modifies the integer prescaler P for finer tuning of the baud rate. The M
value adds in increments of 1/16 of the P value.
The bit time, T
bit
is expressed in terms of the VCLK period T
VCLK
as follows:
For all P other than 0, and all M,
(43)
For P= 0 : T
bit
= 32T
VCLK
Therefore, the LINCLK frequency is given by:
(44)
1366
Serial Communication Interface (SCI)/Local Interconnect Network (LIN) SPNU562–May 2014
Module
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