Datasheet

SCI www.ti.com
28.2.4 SCI Configurations
Before the SCI sends or receives data, its registers should be properly configured. Upon power-up or a
system-level reset, each bit in the SCI registers is set to a default state. The registers are writable only
after the RESET bit is set to 1. Of particular importance is the SWnRST bit. This active-low bit is initialized
to 0 and keeps the SCI in a reset state until it is programmed to 1. Therefore, all SCI configuration should
be completed before a 1 (one) is written to the SWnRST bit.
The following list details the configuration steps that software should perform prior to the transmission or
reception of data. As long as SWnRST is held low the entire time that the SCI is being configured, the
order in which the registers are programmed is not important.
• Enable SCI by setting RESET bit.
• Clear SWnRST to 0 before configuring the SCI.
• Select the desired frame format by programming SCIGCR1.
• Configure the LINRX and LINTX pins for SCI functionality by setting the RX FUNC and TX FUNC bit.
• Select the baud rate to be used for communication by programming BRSR.
• Select internal clock by programming the CLOCK bit.
• Set the CONT bit to make SCI not to halt for an emulation breakpoint until its current reception or
transmission is complete (this bit is used only in an emulation environment).
• Set LOOP BACK bit to connect the transmitter to the receiver internally (this feature is used to perform
a self-test).
• Select the receiver enable RXENA bit if data is to be received.
• Select the transmit enable TXENA bit if data is to be transmitted.
• Set SWnRST to 1 after the SCI is configured.
• Perform Receive or Transmit data (see Section 28.2.4.1 and Section 28.2.4.2).
28.2.4.1 Receiving Data
The SCI receiver is enabled to receive messages if the RX FUNC bit and the RXENA bit are set to 1. If
the RX FUNC bit is not set, the LINRX pin functions as a general purpose I/O pin rather than as an SCI
function pin.
SCI module can receive data in one of the following modes:
• Single-Buffer (Normal) Mode
• Multi-Buffer Mode
After a valid idle period is detected, data is automatically received as it arrives on the LINRX pin.
28.2.4.1.1 Receiving Data in Single-Buffer Mode
Single Buffer Mode is selected when MBUF MODE bit is 0. In this mode SCI sets the RXRDY bit when it
transfers newly received data from SCIRXSHF to SCIRD. The SCI clears the RXRDY bit after the new
data in SCIRD has been read. Also, as data is transferred from SCIRXSHF to SCIRD, the SCI sets FE,
OE, or PE if any of these error conditions were detected in the received data. These error conditions are
supported with configurable Interrupt capability. The wake-up and break-detect status bits are also set if
one of these errors occurs, but they do not necessarily occur at the same time that new data is being
loaded into SCIRD.
You can receive data by:
1. Polling Receive Ready Flag
2. Receive Interrupt
3. DMA
In polling method, software can poll for RXRDY bit and read the data from SCIRD register once RXRDY is
set high. CPU is unnecessarily overloaded by selecting Polling mode. To avoid this, you can use either
Interrupt or DMA method. To use interrupt method SET RX INT bit should be set and to use DMA SET RX
DMA bit should be set. Either an Interrupt or a DMA request is generated the moment RXRDY is set.
1360
Serial Communication Interface (SCI)/Local Interconnect Network (LIN) SPNU562–May 2014
Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated