Datasheet

158
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) The filter width is 6 VCLK3 cycles.
7.1.6.3 Trip Zone TZ5n
This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted
whenever an oscillator failure or a PLL slip is detected on the device. The applciation can use this trip
zone input for each ePWMx module to prevent the external system from going out of control when the
device clocks are not within expected range (system running at limp clock).
The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the
system module. These level signals are set until cleared by the application.
7.1.6.4 Trip Zone TZ6n
This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,
the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the
external system from going out of control when the CPU is stopped.
NOTE
There is a signal called DBGACK that the CPU drives when it enters debug mode. This
signal must be inverted and used as the Debug Mode Entry signal for the trip zone input.
7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
A special scheme is implemented to select the actual signal used for triggering the start of conversion on
the two ADCs on this device. This scheme is defined in Section 7.4.2.3.
7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
Table 7-4. ePWMx Timing Requirements
TEST CONDITIONS MIN MAX UNIT
t
w(SYNCIN)
Synchronization input pulse width
Asynchronous 2 t
c(VCLK3)
cycles
Synchronous 2 t
c(VCLK3)
cycles
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
(1)
cycles
Table 7-5. ePWMx Switching Characteristics
PARAMETER
TEST
CONDITIONS
MIN MAX UNIT
t
w(PWM)
Pulse duration, ePWMx output high or low 33.33 ns
t
w(SYNCOUT)
Synchronization Output Pulse Width 8 t
c(VCLK3)
cycles
t
d(PWM)tza
Delay time, trip input active to PWM forced high, OR
Delay time, trip input active to PWM forced low
No pin load 25 ns
t
d(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z 20 ns
(1) The filter width is 6 VCLK3 cycles.
Table 7-6. ePWMx Trip-Zone Timing Requirements
TEST CONDITIONS MIN MAX UNIT
t
w(TZ)
Pulse duration, TZn input low
Asynchronous 2 * TBePWMx
cyclesSynchronous 2 t
c(VCLK3)
Synchronous with input filter 2 t
c(VCLK3)
+ filter width
(1)