Datasheet

TXRDY
TX EMPTY
SCIFLR.8
SCIFLR.11
TX INT ENA
TX INT
TXWAKE
Address bit
†
Shift register
Transmit buffer
1
8
LINRX
SCIGCR1.24
8
Receive buffer
SCIRD
RXRDY
BRKDT
SCIFLR.9
SCIFLR.0
RX INT ENA
RXWAKE
SCIFLR.12
RX INT
Shift register
WAKEUP
SCIFLR.1
SCITD
SCITXSHF
SCIRXSHF
ERR INT
SCIFLR24:26
SCIGCR1.25
TXENA
SCIFLR.10
BRKDT INT ENA
WAKEUP INT ENA
PE
OE FE
RECEIVER
TRANSMITTER
CLOCK
Baud clock
SCIBAUD
generator
Baud rate
registers
LINTX
RXENA
SCISETINT.9
SCISETINT.0
SCISETINT.1
SCIGCR1.5
SCISETINT.8
SCI
VCLK
Peripheral
Introduction and Features www.ti.com
Figure 28-1. SCI Block Diagram
1346
Serial Communication Interface (SCI)/Local Interconnect Network (LIN) SPNU562–May 2014
Module
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