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MibSPI Pin Timing Parameters

27.6.3 Master Mode Timing Parameter Details

In case of Master, the module drives out SPICLK. It also drives out the Transmit data on SPISIMO with

respect to its internal SPICLK. In case of Master mode, the RX data on SPISOMI pin is registered with

respect to SPICLK recieved through Input buffer from the I/O pad.

If Chip Select pin is functional, then Master will drive out SPISCS pin(s) before starting the SPICLK. If

SPIENA pin is functional, then Master will wait for an active ‘low’ from Slave on the input pin to start the

SPICLK.

27.6.4 Slave Mode Timing Parameter Details

In case of Slave mode, the module will drive only SPISOMI and SPIENA pins. All other pins are inputs to

it. The RX data on SPISIMO pin will be registered with respect to SPICLK pin. Slave will use SPISCS pin

to drive out SPIENA pin if both are functional. If 4pin with SPIENA is configured, then Slave will drive out

active low signal on SPIENA pin when a new data is written to the TX Shift Register. Irrespective of 4pin

with SPIENA or 5pin configuration, the Slave will deassert the SPIENA pin after the last bit is received. If

ENABLE_HIGHZ (SPIINT0.24) bit is 0, the de-asserted value of SPIENA pin will be 1. Otherwise, it will

depend upon the internal PullUp or PullDown resistor (if implemented) depending upon the Specification

of the Chip.

1341

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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