Datasheet

SPIDAT
SPISCS
* ENABLE_HIGHZ is set to ‘1’ in Slave SPI
VCLK
Write to
SPIENA
SPICLK
* Diagram shows relationship between the SPISCS from a Master to SPIENA from Slave SPI when SPIENA is configured in High-Z mode
SPIDAT
SPISCS
* ENABLE_HIGHZ is set to ‘0’ in Slave SPI
VCLK
Write to
SPIENA
SPICLK
* Diagram shows relationship between the SPISCS from a Master to SPIENA from Slave SPI when SPIENA is configured in Push-Pull mode
VCLK
Write to
SPIDAT
SPIENA
SPICLK
* Diagram shows a relationship between the SPIENA from Slave and SPICLK from Master
VCLK
SPICLK
SPISOMI
SPISIMO
* Dotted vertical lines indicate the receive edges
Write to
SPIDAT
MibSPI Pin Timing Parameters www.ti.com
27.6.2 Slave Mode Timings for SPI/MibSPI
Figure 27-97. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration
Figure 27-98. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration
Figure 27-99. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single Slave)
Figure 27-100. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single/Multi-Slave)
1340
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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