Datasheet

.
.
.
TXBUF0
TXBUF1
TXBUF254
TXBUF255
Parity/ECC0
Parity/ECC1
0
31
Address
BASE+0x000h
BASE+0x3FFh
BASE+0x400h
BASE+0x7FFh
.
.
.
.
.
.
TXParity/ECC0
TXParity/ECC1
TXParity/ECC254
TXParity/ECC255
RXParity/ECC0
RXParity/ECC1
RXParity/ECC254
RXParity/ECC255
0
31
Multibuffer RAM
Address
BASE+0x800h
BASE+0xBFFh
BASE+0xC00h
BASE+0xFFFh
Memory organization during Normal Operation
BASE - Base Address of Multibuffer RAM
Refer to specific Device Datasheet
for the actual value of BASE.
*
.
.
Parity/ECC255
Parity/ECC254
.
.
.
RXBUF0
RXBUF1
RXBUF254
RXBUF255
0
31
(Parity/ECC locations are not accessible by CPU)
Parity/ECC0
Parity/ECC1
.
.
Parity/ECC255
Parity/ECC254
Parity/ECC memory organization during Test Mode
www.ti.com Parity\ECC Memory
Figure 27-90. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF
Mode is Enabled
1335
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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