Datasheet

N2HET1 N2HET2
ePWM1
2 VCLK3 cycles
Pulse Stretch
EPWM1SYNCI
SYNCI
EXT_LOOP_SYNCN2HET1_LOOP_SYNC
double
sync
PINMMR165[24]=0 and PINMMR165[25]=1
6 VCLK3
Cycles Filter
156
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
The connection between the NHET1_LOOP_SYNC and the SYNCI input of ePWM1 module is
implemented as shown in Figure 7-3.
Figure 7-3. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules
7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is implemented as PINMMR166[1] register bit 1.
When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default
condition.
When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.
For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must
be set identically. The proper procedure for enabling the ePWM clocks is as follows:
• Each ePWM is individually associated with a power down bit in the PSPWRDWNCLRx register of the PCR2
module. Enable the individual ePWM module clocks (if disable) using the control registers in the PCR2.
• Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
• Configure the prescaler values and desired ePWM modes.
• Configure TBCLKSYNC = 1.
7.1.5 ePWM Synchronization with External Devices
The output sync from the ePWM1 module is also exported to the I/O Mux such that multiple devices can
be synchronized together. The signal pulse must be stretched by 8 VCLK3 cycles before being exported
on the IO Mux pin as the ePWMSYNCO signal.