Datasheet

Multi-buffer RAM www.ti.com
Table 27-60. Multi-buffer RAM Transmit Data Register Field Descriptions (continued)
Bit Field Value Description
26 WDEL Enable the delay counter at the end of the current transaction.
Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored.
0 No delay will be inserted. However, SPISCS pins will still be de-activated for at least for 2VCLK
cycles if CSHOLD = 0.
Note: The duration for which the SPISCS pin remains deactivated also depends upon the time
taken to supply a new word after completing the shift operation (in compatibility mode). If TXBUF is
already full, then the SPISCS will be deasserted for at least two VCLK cycles (if WDEL = 0).
1 After a transaction, WDELAY of the corresponding data format will be loaded into the delay
counter. No transaction will be performed until the WDELAY counter overflows. The SPISCS pins
will be de-activated for at least (WDELAY + 2) * VCLK_Period duration.
25-24 DFSEL Data word format select
0 Data word format 0 is selected
1h Data word format 1 is selected
2h Data word format 2 is selected
3h Data word format 3 is selected
23-16 CSNR 0-FFh Chip select number. CSNR defines the chip-select that will be activated during the data transfer.
Note: Writing to only the control field (using byte writes) does not initiate any SPI transfer in
master mode. This feature can be used to set up SPICLK phase or polarity before actually
starting the transfer by only updating the DFSEL fields in the control field to select the
required phase/polarity combination.
15-0 TXDATA 0-7FFFh Transfer data.When written, these bits are copied to the shift register if it is empty. If the shift
register is not empty, then they are held in TXBUF.
SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the lower
16 bits of SPIDAT1 to 0.
Write to this register ONLY when using the automatic slave chip-select feature (see
Section 27.2.1.1 for more information). A write to this register will drive the contents of CSNR[7:0]
on the SPISCS[3:0] pins, if they are configured as functional pins.
When this register is read, the contents of TXBUF, which holds the latest data written, will be
returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.
1330
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated