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Control Registers

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27.3.48 Single Bit Error Address Register - TXRAM (SBERRADDR0)

Figure 27-84. Single Bit Error Address Register - TXRAM (SBERRADDR0) [offset = 14Ch]

31 16

Reserved

R-0

15 11 10 0

Reserved SBERRADDR0

R-0 RC-0

LEGEND: R = Read only; RC = Read to clear; -n = value after reset

Table 27-58. Single Bit Error Address Register - TXRAM (SBERRADDR0) Field Descriptions

Bit Field Value Description

31-11 Reserved 0 Read returns 0. Writes have no effect.

10-0 SBERRADDR0 This register holds the address when a single bit error is generated from SECDED block while

reading the MibSPI (Transmit) TXRAM. The TXRAM can be read either by CPU or by the

MibSPI Sequencer logic for transmission. This error address is frozen from being updated until

it is read by the VBUSP host.

Reading this register clears its contents to the default value of 0x000. Writes to this register are

ignored.

NOTE: SBERRADDR0 values

The offset address of TXRAM can vary from 000h-1FFh, if EXTENDED_BUF mode is

disabled. If the EXTENDED_BUF mode is enabled, the offset address can vary from 000h-

3FFh.

The register does not clear its contents during and after any of the module level reset, System level resets

or even Power-up Reset. A Read operation to this register clears its contents to all 0s.

NOTE: A read to SBERRADDR0 register will clear the SBE_FLG0 in PAR_ECC_STAT register.

However, in emulation mode (VBUSP_EMUDBG = 1), the read to SBERRADDR0 register

does not clear the corresponding SBE_FLG0.

After a power-up reset the contents of this register will be unpredictable. So, a read operation can be

performed after power-up to clear its contents if required. Contents of this register are meaningful only

when SBE_FLG0 is set to 1.

NOTE: Clearing of SBERR status and address registers

After completing a memory test sequence, specifically where ECC features are tested, user

must read back the status flags in ECC_STAT and SBERRADDRx registers to ensure that

they are in normal clear state by reading/writing appropriately. This can be performed before

the start of a normal multi-buffer mode transactions as well.

NOTE: When ECC is supported, SBERRADDR0 will indicate only word address.

SBERRADDR0[1:0] will always be 00.

1326

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

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