Datasheet

TZxn
(x = 1, 2, or 3)
ePWMx
double
sync
(x = 1 through 7)
6 VCLK3
Cycles Filter
155
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Figure 7-2 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double synchronous + filter width) for ePWMx.
Figure 7-2. ePWMx Input Synchronization Selection Detail
7.1.1 ePWM Clocking and Reset
Each ePWM module has a clock enable (ePWMxENCLK) which is controlled by its respective Peripheral
Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the peripherals,
the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register in the
system module. In additional, the peripherals must be released from their power down state by clearing
their respective bit in the PSPWRDWNCLRx register. By default after reset, the peripherals are in
powerdown state.
Table 7-1. ePWMx Clock Enable Control
ePWM MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
ePWM1 PSPWRDWNCLR3[16] 1
ePWM2 PSPWRDWNCLR3[17] 1
ePWM3 PSPWRDWNCLR3[18] 1
ePWM4 PSPWRDWNCLR3[19] 1
ePWM5 PSPWRDWNCLR3[12] 1
ePWM6 PSPWRDWNCLR3[13] 1
ePWM7 PSPWRDWNCLR3[14] 1
7.1.2 Synchronization of ePWMx Time-Base Counters
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-1 shows the
synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or
ignore the synchronization input. For more information, see the ePWM module chapter of the device-
specific TRM.