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27.3.46 ECC Diagnostic Status Register (ECCDIAG_STAT)
NOTE: ECCDIAG_STAT Validity
Both SEFLG[1:0] and DEFLG[1:0] are valid only during Diagnostic Mode (when
ECCDIAG_EN = 5h). This status register should be write-cleared after coming out of
Diagnostic Mode.
Figure 27-82. ECC Diagnostic Status Register (ECCDIAG_STAT) [offset = 144h]
31 18 17 16
Reserved DEFLG
R-0 R/W1C-0
15 2 1 0
Reserved SEFLG
R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Clear type flag; -n = value after reset
Table 27-56. ECC Diagnostic Status Register (ECCDIAG_STAT) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Read returns 0. Writes have no effect.
17 DEFLG[1] Double bit error flag.
0 Read: No error
Write: No effect.
1 Read: A double bit Error is detected for RXRAM bank during diagnostic mode tests.
Write: Clears the bit.
16 DEFLG[0] Double bit error flag.
0 Read: No error
Write: No effect.
1 Read: A double bit Error is detected for TXRAM bank during diagnostic mode tests.
Write: Clears the bit.
15-2 Reserved 0 Read returns 0. Writes have no effect.
1 SEFLG[1] Single bit error flag.
0 Read: No error
Write: No effect.
1 Read: A single bit Error is detected for RXRAM bank during diagnostic mode tests.
Write: Clears the bit.
0 SEFLG[0] Single bit error flag.
0 Read: No error
Write: No effect.
1 Read: A single bit Error is detected for TXRAM bank during diagnostic mode tests.
1 Write: Clears the bit.
1324
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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