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27.3.44 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and

SPIFMT3)

This register provides an extended Prescale values for SPICLK generation to be able to interface with

much slower SPI Slaves. This is an extension of SPIFMT2 and SPIFMT3 registers. For example,

EPRESCALE_FMT3(7:0) of EXTENDED_PRESCALE2 and PRESCALE3(7:0) of SPIFMT3 register will

always reflect the same contents. Similarly EPRESCALE_FMT2(7:0) and PRESCALE2(7:0) of SPIFMT2

reflect the same contents.

Figure 27-80. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and

SPIFMT3) [offset = 13Ch]

31 27 26 16

Reserved EPRESCALE_FMT3

R-0 R/WP-0

15 11 10 0

Reserved EPRESCALE_FMT2

R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 27-54. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions

Bit Field Value Description

31-27 Reserved 0 Read returns 0. Writes have no effect.

26-16 EPRESCALE_FMT3 0-7FFh EPRESCALE_FMT3. Extended Prescale value for SPIFMT1. EPRESCALE_FMT1

determines the bit transfer rate of data format 3 if the SPI/MibSPI is the network

master. EPRESCALE_FMT3 is use to derive SPICLK from VCLK. If the SPI is

configured as slave, EPRESCALE_FMT3 does not need to be configured. These

EPRESCALE_FMT3(7:0) bits and PRESCALE3(7:0) bits of SPIFMT1 register will point

to the same physically implemented register. The clock rate for data format 1 can be

calculated as:

Format3

= VBUSPCLK / (EPRESCALE_FMT3 + 1)

Write: This register field should be written if a SPICLK prescaler of more

VBUSPCLK/256 is required. This field provides a prescaler of up to VBUSPCLK/2048

for SPICLK. Writing to this register field will also get reflected in SPIFMT3(15:8).

Read: Reading this field will reflect the PRESCALE value based on the last written

Note: If Extended Prescaler is required, it should be ensured that

EXTENDED_PRESCALE2 register is programmed after SPIFMT3 register is

programmed. This is to ensure that the final SPICLK prescale value is controlled

by EXTENDED_PRESCALE2 register when a prescale of more 256 is intended on

SPICLK. Writing to PRESCALE3 field of SPIFMT3 will automatically clear

EPRESCALE_FMT3(10:8) bits to ‘000’ so that the integrity of PRESCALE value is

maintained.

15-11 Reserved 0 Read returns 0. Writes have no effect.

1322

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

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