Datasheet

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27.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR)
This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog.
In addition, it contains control bits to induce error conditions into the module. These are to be used only for
module testing.
All of the control/status bits in this register are valid only when the IOLPBKTSTENA field is set to Ah.
Figure 27-78. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]
31 25 24
Reserved SCS FAIL FLG
R-0 R/W1C-0
23 21 20 19 18 17 16
Reserved CTRL CTRL CTRL CTRL CTRL
BITERR DESYNC PARERR TIMEOUT DLENERR
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
15 12 11 8
Reserved IOLPBKTSTENA
R-0 R/WP-0
7 6 5 3 2 1 0
Reserved ERR SCS PIN CTRL SCS LPBKTYPE RXPENA
PINERR
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privilege mode only; -n = value after reset
Table 27-52. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Read returns 0. Writes have no effect.
24 SCS FAIL FLG Bit indicating a failure on SPISCS pin compare during analog loopback.
0 Read: No miscompares occurred on any of the eight chip select pins (vs. the internal
chip select number CSNR during transfers).
Write: Writing a zero to this bit has no effect.
1 Read: A comparison between the internal CSNR field and the analog looped-back
value of one or more of the SPISCS[3:0] pins failed. A stuck-at fault is detected on one
of the SPISCS[3:0]. Comparison is done only on the pins that are configured as
functional and during transfer operation.
Write: This flag bit is cleared.
23-21 Reserved 0 Read returns 0. Writes have no effect.
20 CTRL BITERR Controls inducing of BITERR during I/O loopback test mode.
0 Do not interfere with looped-back data.
1 Induces bit errors by inverting the value of the incoming data during loopback.
19 CTRL DESYNC Controls inducing of the desync error during I/O loopback test mode.
0 Do not cause a desync error.
1 Induce a desync error by forcing the incoming SPIENA pin (if functional) to remain 0
even after the transfer is complete. This forcing will be retained until the kernel reaches
the idle state.
18 CTRL PARERR Controls inducing of the parity errors during I/O loopback test mode.
0 Do not cause a parity error.
1 Induce a parity error by inverting the polarity of the parity bit.
17 CTRL TIMEOUT Controls inducing of the timeout error during I/O loopback test mode.
0 Do not cause a timeout error.
1 Induce a timeout error by forcing the incoming SPIENA pin (if functional) to remain 1
when transmission is initiated. The forcing will be retained until the kernel reaches the
idle state.
1318
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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