Datasheet

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Control Registers

Table 27-48. Effect of BIG_ENDIAN Port on UERRADDR1[1:0] Bits

Endianness

Fault Location is Among the RAM Bits

1 (Big Endian) 0 (Little Endian)

00 11 7:0

01 10 15:8

UERRADDR1[1:0]

10 01 23:16

11 00 31:24

NOTE: When ECC is supported, UERRADDR0 will indicate only word address. UERRADDR0[1:0]

will always be 00.

1315

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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