Datasheet

TZ1/2/3n
SOCA1, SOCB1
EPWM1INTn
EPWM1TZINTn
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
Debug Mode Entry
OSC FAIL or PLL Slip
IOMUX
EPWMSYNCI
ePWM1
eCAP1
EPWM1A
EPWM1B
EPWM2/3/4/5/6A
EPWM2/3/4/5/6B
ePWM7
EPWM7A
ECAP1
Pulse
Stretch,
8 VCLK3
cycles
EPWM1SYNCO
(after stretch)
ADC Wrapper
VBus32 / VBus32DP
EPWM1ENCLK
TBCLKSYNC
VIM
VCLK3, SYS_nRST
EPWM2/3/4/5/6ENCLK
TBCLKSYNC
EPWM7ENCLK
TBCLKSYNC
ECAP1INTn
ePWM
2/3/4/5/6
VIM
EQEP1 + EQEP2
EPWM7B
CPU
System Module
TZ6n
TZ5n
TZ4n
VCLK3, SYS_nRST
TZ1/2/3n
TZ1/2/3n
Debug Mode Entry
OSC FAIL or PLL Slip
TZ6n
TZ5n
TZ4n
Debug Mode Entry
OSC FAIL or PLL SLip
TZ6n
TZ5n
TZ4n
SOCA2/3/4/5/6
SOCB2/3/4/5/6
EPWM2/3/4/5/6INTn
EPWM2/3/4/5/6TZINTn
EPWM7INTn
EPWM7TZINTn
VBus32
VBus32
VCLK3, SYS_nRST
VBus32
VIM
ADC Wrapper
VIM
EQEP1 + EQEP2
CPU
System Module
VIM
ADC Wrapper
VIM
EQEP1 + EQEP2
CPU
System Module
VIM
Mux
Selector
Mux
Selector
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
SOCA7, SOCB7
Mux
Selector
NHET1_LOOP_SYNC
EPWM1SYNCO (before stretch)
SYNCI
SYNCO
see Note A
see Note A
see Note A
154
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
7 Peripheral Information and Electrical Specifications
7.1 Enhanced Translator PWM Modules (ePWM)
Figure 7-1 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.
A. For more detail on the ePWMx input synchronization selection, see Figure 7-2.
Figure 7-1. ePWMx Module Interconnections