Datasheet

Control Registers www.ti.com
27.3.39 Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM
(UERRADDR1)
Figure 27-75. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM
(UERRADDR1) [offset = 128h]
31 16
Reserved
R-0
15 11 10 0
Reserved UERRADDR1
R-0 RC-x
LEGEND: R/W = Read/Write; R = Read only; RC = Read to clear; -n = value after reset
Table 27-47. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM
(UERRADDR1) Field Descriptions
Bit Field Value Description
31-11 Reserved 0 Read returns 0. Writes have no effect.
10-0 UERRADDR1 Uncorrectable Parity or double bit ECC error address This register holds the address of the
RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive)
RXRAM. The address captured is byte aligned when RAM Parity Check is supported. This error
address is frozen from being updated until it is read by the VBUS host.
Reading this register clears its contents to the default value. The default value is 400h if
Extended Buffer feature is enabled; else, it is 200h. Writes to this register are ignored.
NOTE: UERRADDR1 values
The offset address of RXRAM can vary from 000h-1FFh, if EXTENDED_BUF mode is
disabled. If the EXTENDED_BUF mode is enabled, the offset address can vary from 000h-
3FFh.
The register does not clear its contents during and after any of the module level reset, System level resets
or even Power-up Reset.
NOTE: A read to UERRADDR1 register will clear the UERR_FLG1 in PAR_ECC_STAT register.
However, in emulation mode (VBUSP_EMUDBG = 1), the read to UERRADDR1 register
does not clear the corresponding UERR_FLG1.
After a power-up reset the contents of this register will be unpredictable. So, a read operation can be
performed after power-up to clear its contents if required. Contents of this register are meaningful only
when UERR_FLG1 is set to 1.
If ECC feature is implemented, the Sequencer FSM clearing the TXFULL flag (after a TXRAM location
read out and written to the shift register for transfer) will trigger read-modify-write operation to the RXRAM.
Similarly, each time FSM reads a TXRAM to transfer it out, the corresponding RXRAM location is also
automatically read to determine the status of the buffer. A double bit error could be detected during these
FSM read operations and result in error address and flags getting captured.
NOTE: Clearing of UERR status and address registers
After completing a memory test sequence, specifically where parity or ECC features are
tested, user must read back the status flags in PAR_ECC_STAT and UERRADDRx registers
and ensure that they are in normal clear state by reading/writing appropriately. This can be
performed before the start of a normal multi-buffer mode transactions as well.
If RAM Parity Check is supported, UERRADDR1[1:0] values will reflect the byte positions of failed byte
based on the following scheme to take care of Endianness of memory organization.
1314
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated