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Control Registers

27.3.36 DMA Large Count (DMACNTLEN)

Figure 27-72. DMA Large Count Register (DMACNTLEN) [offset = 118h]

31 16

Reserved

R-0

15 1 0

Reserved LARGE COUNT

R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 27-44. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions

Bit Field Value Description

31-1 Reserved 0 Read returns 0. Writes have no effect.

0 LARGE COUNT Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL.

0 Select the DMAxCTRL counters.Writes to the DMAxCTRL register will modify the ICOUNT

value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The

DMAxCOUNT register should not be used since any write to this register will be overwritten by

a subsequent write to the DMAxCTRL register to set the TXDMAENA or RXDMAENA bits.

1 Select the DMAxCOUNT counters.Writes to the DMAxCTRL register will not modify the

ICOUNT value. The ICOUNT value must be written to in the DMAxCOUNT register before the

RXDMAENA or TXDMAENA bits are set in the DMAxCTRL register. The DMAxCOUNT register

should be used for reading COUNT or ICOUNT.

1311

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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