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Control Registers

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27.3.35 DMAxCOUNT Register (ICOUNT)

NOTE: These registers are used only if the LARGE COUNT bit in the DMACNTLEN register is set.

The number of bidirectional DMA channels varies by device. The number of DMA channels

and hence the number of DMA registers varies by device.

Figure 27-71. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h]

31 16

ICOUNTx

R/W-0

15 0

COUNTx

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27-43. MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions

Bit Field Value Description

31-16 ICOUNTx 0-FFFFh Initial number of DMA transfers. ICOUNTx is used to preset the transfer counter COUNTx.

Every time COUNTx hits zero, it is reloaded with ICOUNTx. The real number of transfer equals

ICOUNTx plus one. If ONESHOTx is set, ICOUNTx defines the number of DMA transfers that

are performed before the MibSPI automatically disables the corresponding DMA channel. If

NOBRKx is set, ICOUNTx defines the number of DMA transfers that are performed in one

sequence without a transfer from any other buffer

15-0 COUNTx 0-FFFFh The actual number of remaining DMA transfers.COUNTx Contains the actual number of

DMA transfers that remain, until the DMA channel is disabled, if ONESHOTx is set. Since the

real counter value is always ICOUNTx +1, the 17th bit of COUNTx is available on

DMACTRLx[6] bit.

Note: Usage Tip for Block Transfer Using a Single DMA Request. It is possible to use the

multi-buffer RAM to transfer chunks of data to/from an external SPI. A DMA Controller

can be used to handle the data in bursts. Suppose a chunk of 64 bytes of data needs to

be transferred and a single DMA request needs to be generated at the end of transferring

the 64 bytes. This can be easily achieved by configuring a TG register for the 64 buffer

locations and using the DMAxCTRL/DMAxCOUNT registers to configure the last buffer

(64th) of the TG as the BUFID and enable RXDMA (NOBRK = 0). At the end of the transfer

of the 64th buffer, a DMA request will be generated on the selected DMA request

channel. The DMA controller can do a burst read of all 64 bytes from RXRAM and/or then

do a burst write to all 64 bytes to the TXRAM for the next chunk.

1310

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

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