Datasheet

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Table 27-42. DMA Channel Control Register (DMAxCTRL) Field Descriptions (continued)
Bit Field Value Description
14 TXDAMENAx Transmit data DMA channel enable.
0 No DMA request upon new transmit data.
1 The physical DMA channel for the transmit path is enabled. The first DMA request pulse is
generated right after setting TXDMAENAx to load the first transmit data. The buffer should
be configured in the as "skip until TXFULL is set" or "suspend to wait until TXFULL is set" in
order to ensure synchronization between the DMA controller and the MibSPI sequencer.
13 NOBRKx Non-interleaved DMA block transfer. This bit is available in master mode only.
Note: Special Conditions during a NOBRK Buffer Transfer. If a NOBRK DMA buffer is
currently being serviced by the sequencer, then it is not allowed to be disabled
prematurely.
During a NOBRK transfer, the following operations are not allowed:
• Clearing the NOBRKx bit to 0
• Clearing the RXDMAENAx to 0 (if it is already 1)
• Clearing the TXDMAENAx to 0 (if it is already 1)
• Clearing the BUFMODE[2:0] bits to 000
Any attempts to perform these actions during a NOBRK transfer will produce
unpredictable results.
0 DMA transfers through the buffer referenced by BUFIDx are interleaved by data transfers
from other active buffers or TGs. Every time the sequencer checks the DMA buffer, it
performs one transfer and then steps to the next buffer.
1 NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced
by BUFIDx without a data transfer from any other buffer. The sequencer remains at the
DMA buffer until ICOUNTx+1 transfers have been processed.For example, this can be used
to generate a burst transfer to one device without disabling the chip select signal in-between
(the concerned buffer has to be configured with CSHOLD=1). Another example would be to
have a defined block data transfer in slave mode, synchronous to the master SPI.
Note: Triggering of higher priority TGs or enabling of higher priority DMA channels
will not interrupt a NOBRK block transfer.
12-8 ICOUNTx 0-1Fh Initial count of DMA transfers. ICOUNTx is used to preset the transfer counter
COUNTx[4:0]. Every time COUNTx hits zero it is reloaded with ICOUNTx. The real number
of transfers equals ICOUNTx plus one.
If ONESHOTx is set, ICOUNTx defines the number of DMA transfers that are performed
before the MibSPI automatically disables the DMA channels. If NOBRKx is set, ICOUNTx
defines the number of DMA transfers that are performed in one sequence without a transfer
from any other buffer.
Note: See Section 27.3.35 (ICOUNT) and Section 27.3.36 (DMACNTLEN) about how to
increase the ICOUNT to a 16-bit value. With this extended capability, MibSPI can
transfer a block of up to 65535 (65K) words without interleaving (if NOBRK is used) or
without deasserting the chip select between the buffers (if CSHOLD is used).
7 Reserved 0 Read returns 0. Writes have no effect.
6 COUNT BIT17x The 17th bit of the COUNT field of DMAxCOUNT register.
5-0 COUNTx 0-3Fh Actual number of remaining DMA transfers. This field contains the actual number of DMA
transfers that remain, until the DMA channel is disabled, if ONESHOTx is set.
Note: If the TX and RX DMA requests are enabled, the COUNT register will be
decremented when the RX has been serviced.
1309
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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