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27.3.34 DMA Channel Control Register (DMAxCTRL)
Each DMA channel can be configured via one dedicated control register. The register description below
shows one exemplary control register that is identical for all DMA channels; for example, the control
register for DMA channel 0 is named DMA0CTRL. The MibSPI supports up to 8 bidirectional DMA
channels.
The number of bidirectional DMA channels varies by device. The number of DMA channels and hence the
number of DMA channel control registers may vary.
Figure 27-70. DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h]
31 30 24 23 20 19 16
ONESHOT BUFID RXDMA_MAP TXDMA_MAP
R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 8
RXDMAENA TXDMAENA NOBRK ICOUNT
R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 0
Reserved COUNT BIT17 COUNT
R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27-42. DMA Channel Control Register (DMAxCTRL) Field Descriptions
Bit Field Value Description
31 ONESHOT Auto-disable of DMA channel after ICOUNT+1 transfers.
0 The length of the block transfer is fully controlled by the DMA controller. The enable bits
RXDMAENAx and TXDMAENAx are not modified by the MibSPI.
1 ONESHOT allows a block transfer of defined length (ICOUNTx+1), mainly controlled by the
MibSPI and not by the DMA controller. After ICOUNTx +1 transfers, the enable bits
RXDMAENAx and TXDMAENAx are automatically cleared by the MibSPI, hence no more
DMA requests are generated. In conjunction with NOBRKx, a burst transfer can be initiated
without any other transfer through another buffer.
30-24 BUFIDx 0-7Fh Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA
transfer. In order to synchronize the transfer with the DMA controller with the NOBRK
condition the "suspend to wait until..." modes must be used.
23-20 RXDMA_MAPx 0-Fh Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA
controller. One request line for receive data and the other for request line for transmit data.
RXDMA_MAPx[3:0] defines the number of the physical DMA Request line that is connected
to the receive path of the MibSPI DMA channel.
If RXDMAENAx and TXDMAENAx are both set to "˜1', then RXDMA_MAPx[3:0] shall differ
from TXDMA_MAPx[3:0] and shall differ from any other used physical DMA Request line.
Otherwise unexpected interference may occur.
19-16 TXDMA_MAPx 0-Fh Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA
controller. One request line for receive data and the other for request line for transmit data.
TXDMA_MAPx[3:0] defines the number of the physical DMA Request line that is connected
to the transmit path of the MibSPI DMA channel.
If RXDMAENAx and TXDMAENAx are both set then TXDMA_MAPx[3:0] shall differ
fromRXDMA_MAPx[3:0] and shall differ from any other used physical DMA Request line.
Otherwise unexpected interference may occur.
15 RXDMAENAx Receive data DMA channel enable.
0 No DMA request upon new receive data.
1 The physical DMA channel for the receive path is enabled. The first DMA request pulse is
generated after the first transfer from the referenced buffer (BUFIDx) is finished. The buffer
should be configured in as "skip until RXEMPTY is set" or "suspend to wait until RXEMPTY
is set" in order to ensure synchronization between the DMA controller and the MibSPI
sequencer.
1308
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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