Datasheet

www.ti.com

Control Registers

27.3.29 Transfer Group Interrupt Level Clear Register (TGITLVCR)

The register TGITLVCR clears the level of interrupts for transfer completed interrupt and for transfer

suspended interrupt to level 0.

The register map shown in Figure 27-64 and Table 27-37 represents a super-set device with the

maximum number of TGs (16) assumed. The actual number of bits available varies per device.

Figure 27-64. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]

31 16

CLRINTLVLRDY

R/W-0

15 0

CLRINTLVLSUS

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27-37. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions

Bit Field Value Description

31-16 CLRINTLVLRDY Transfer-group completed interrupt level clear.

0 Read: The TGx-completed interrupt is set to INT0.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-completed interrupt is set to INT1.

Write: Set the TGx-completed interrupt to INT0.

15-0 CLRINTLVLSUS Transfer group suspended interrupt level clear.

0 Read: TGx-suspended interrupt is set to INT0.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-suspended interrupt is set to INT1.

Write: Set the TG-x suspended interrupt INT0.

1301

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

Submit Documentation Feedback