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Control Registers

27.3.27 TG Interrupt Enable Clear Register (TGITENCR)

The register TGITENCR is used to clear the interrupt enables for the TG-completed interrupt and the TG-

suspended interrupts.

The register map shown in Figure 27-62 and Table 27-35 represents a super-set device with the

maximum number of TGs (16) assumed. The actual number of bits available varies per device.

Figure 27-62. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h]

31 16

CLRINTENRDY

R/W-0

15 0

CLRINTENSUS

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27-35. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions

Bit Field Value Description

31-16 CLRINTENRDY TG interrupt clear (disabled) when transfer finished.

0 Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when

TGx completes.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx

completes.

Write: Disable the TGx-completed interrupt. The interrupt gets generated when TGx completes.

15-0 CLRINTENSUS TG interrupt clear (disabled) when transfer suspended.

0 Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when

TGx is suspended.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx is

suspended.

Write: Disable the TGx-completed interrupt. The interrupt gets generated when TGx is

suspended.

1299

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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