Datasheet

Control Registers

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27.3.26 TG Interrupt Enable Set Register (TGITENST)

The register TGITENST contains the TG interrupt enable flags for transfer-finished and for transfer-

suspended events. Each of the enable bits in the higher half-word and the lower half-word of TGITENST

belongs to one TG.

The register map shown in Figure 27-61 and Table 27-34 represents a super-set device with the

maximum number of TGs (16) assumed. The actual number of bits available varies per device.

Figure 27-61. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]

31 16

SETINTENRDY

R/W-0

15 0

SETINTENSUS

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27-34. TG Interrupt Enable Set Register (TGITENST) Field Descriptions

Bit Field Value Description

31-16 SETINTENRDY TG interrupt set (enable) when transfer finished.

0 Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when

TGx completes.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx

completes.

Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx completes.

15-0 SETINTENSUS TG interrupt set (enabled) when transfer suspended

0 Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when

TGx is suspended.

Write: A write of 0 to this bit has no effect.

1 Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx is

suspended.

Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx is

suspended.

1298

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

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