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1521

Control Registers

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Table 27-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions (continued)

Bit Field Value Description

12-10 MMODE1 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if

modulo option is supported by the module).

0 1-data line mode - default (PMODE should be set to 00)

1h 2-data line mode (PMODE should be set to 00)

2h 3-data line mode (PMODE should be set to 00)

3h 4-data line mode (PMODE should be set to 00)

4h 5-data line mode (PMODE should be set to 00)

5h 6-data line mode (PMODE should be set to 01)

6h-7h Reserved

9-8 PMODE1 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines.

0 0 = normal operation/1-data line (MMODE should be set to 000)

1h 1h = 2-data line mode (MMODE should be set to 000)

2h 2h = 4-data line mode (MMODE should be set to 000)

3h 3h = 8-data line mode (MMODE should be set to 000)

7-6 Reserved 0 Read returns 0. Writes have no effect.

5 MODCLKPOL0 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo

mode only. If the MMODE[2:0] bits are 000, this bit will be ignored.

0 Normal SPICLK in all the modes.

1 Polarity of the SPICLK will be inverted if Modulo mode is selected.

4-2 MMODE0 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if