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Control Registers
Table 27-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Read returns 0. Writes have no effect.
29 MODCLKPOL3 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE[2:0] bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
28-26 MMODE3 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0 Normal single dataline mode - Default (PMODE should be set to 00)
1h 2-data line mode (PMODE should be set to 00)
2h 3-data line mode (PMODE should be set to 00)
3h 4-data line mode (PMODE should be set to 00)
4h 5-data line mode (PMODE should be set to 00)
5h 6-data line mode (PMODE should be set to 01)
6h-7h Reserved
25-24 PMODE3 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines.
0 0 = normal operation/1-data line (MMODE should be set to 000)
1h 1h = 2-data line mode (MMODE should be set to 000)
2h 2h = 4-data line mode (MMODE should be set to 000)
3h 3h = 8-data line mode (MMODE should be set to 000)
23-22 Reserved 0 Read returns 0. Writes have no effect.
21 MODCLKPOL2 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE[2:0] bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
20-18 MMODE2 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0 000 = 1-data line Mode - Default (PMODE should be set to 00)
1h 001 = 2-data line Mode (PMODE should be set to 00)
2h 3-data line mode (PMODE should be set to 00)
3h 4-data line mode (PMODE should be set to 00)
4h 5-data line mode (PMODE should be set to 00)
5h 6-data line mode (PMODE should be set to 01)
6h-7h Reserved
17-16 PMODE2 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines.
0 0 = normal operation/1-data line (MMODE should be set to 000)
1h 1h = 2-data line mode (MMODE should be set to 000)
2h 2h = 4-data line mode (MMODE should be set to 000)
3h 3h = 8-data line mode (MMODE should be set to 000)
15-12 Reserved 0 Read returns 0. Writes have no effect.
13 MODCLKPOL1 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE[2:0] bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
1295
SPNU562May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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