Datasheet

HCLK
DMMCLK
DMMSYNC
DMMDATA
DMMnENA
D00 D01 D10 D11 D20 D21 D30 D31 D40 D41 D50
DMMSYNC
DMMCLK
DMMDATA
t
ssu(DMM)
t
sh(DMM)
t
dsu(DMM)
t
dh(DMM)
152
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Figure 6-36. DMMDATA Timing
Figure 6-37 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data
width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up
of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been
received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,
D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets
immediately (after 0 HCLK cycles).
Figure 6-37. DMMnENA Timing