Datasheet

Control Registers www.ti.com
NOTE: Reading from the INTVECT1 register when "Transmit Empty" is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the "Transmit Empty" interrupt.
NOTE: In multi-buffer mode, INTVECT1 contains the interrupt for the highest priority transfer group.
A read from INTVECT1 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to get
loaded into SUSPEND1. The transfer group with the lowest number has the highest priority,
and the transfer group with the highest number has the lowest priority.
Reading the INTVECT1 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRN
interrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRN
flag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).
27.3.24 Parallel/Modulo Mode Control Register (SPIPMCTRL)
NOTE: Do not configure MODCLKPOLx and MMODEx bits since this device does not support
modulo mode.
NOTE: The bits of this register are used in conjunction with the SPIFMTx registers. Each byte of this
register corresponds to one of the SPIFMTx registers.
1. Byte0 (Bits 7:0) are used when SPIFMT0 register is selected by DFSEL[1:0] = 00 in the
control field of a buffer.
2. Byte1 (Bits 15:8) are used when SPIFMT1 register is selected by DFSEL[1:0] = 01 in the
control field of a buffer.
3. Byte2 (Bits 23:16) are used when SPIFMT2 register is selected by DFSEL[1:0] = 10 in the
control field of a buffer.
4. Byte3 (Bits31:24) are used when SPIFMT3 register is selected by DFSEL[1:0] = 11 in the
control field of a buffer.
Figure 27-59. Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch]
31 30 29 28 26 25 24
Reserved MODCLKPOL3 MMODE3 PMODE3
R-0 R/WP-0 R/WP-0 R/WP-0
23 22 21 20 18 17 16
Reserved MODCLKPOL2 MMODE2 PMODE2
R-0 R/WP-0 R/WP-0 R/WP-0
15 14 13 12 10 9 8
Reserved MODCLKPOL1 MMODE1 PMODE1
R-0 R/WP-0 R/WP-0 R/WP-0
7 6 5 4 2 1 0
Reserved MODCLKPOL0 MMODE0 PMODE0
R-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
1294
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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