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27.3.22 Interrupt Vector 0 (INTVECT0)
NOTE: The TG interrupt is not available in MibSPI in compatibility mode. Therefore, there is no
possibility to access this register in compatibility mode.
Figure 27-57. Interrupt Vector 0 (NTVECT0) [offset = 60h]
31 16
Reserved
R-0
15 6 5 1 0
Reserved INTVECT0 SUSPEND0
R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27-30. Transfer Group Interrupt Vector 0 (INTVECT0)
Bit Field Value Description
31-6 Reserved 0 Read returns 0. Writes have no effect.
5-1 INTVECT0 INTVECT0. Interrupt vector for interrupt line INT0.
Returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupt is
pending, INTVECT0 always references the highest prior interrupt source first.
Note: This field reflects the status of the SPIFLG register in vector format. Any updates to
the SPIFLG register will automatically cause updates to this field.
0 There is no pending interrupt.
1h ÷ x Transfer group x (x=0,..,15) has a pending interrupt. SUSPEND0 reflects the type of interrupt
(suspended or finished).
11h Error Interrupt pending. The lower half of SPIFLG contains more details about the type of error.
13h The pending interrupt is a "Receive Buffer Overrun" interrupt.
12h SPI mode: The pending interrupt is a "Receive Buffer Full" interrupt.
Mib mode: Reserved. This bit combination should not occur.
14h SPI mode: The pending interrupt is a "Transmit Buffer Empty" interrupt.
Mib mode: Reserved. This bit combination should not occur.
All Other SPI mode: Reserved. These bit combinations should not occur.
Combinations
0 SUSPEND0 Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT0 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT0 is updated with the vector coming next in the priority
chain.
0 The interrupt type is a "transfer finished" interrupt. In other words, the buffer array referenced by
INTVECT0 has asserted an interrupt because all of data from the transfer group has been
transferred.
1 The interrupt type is a "transfer suspended" interrupt. In other words, the transfer group referenced
by INTVECT0 has asserted an interrupt because the buffer to be transferred next is in "suspend-
to-wait" mode.
NOTE: Reading from the INTVECT0 register when "Transmit Empty" is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the "Transmit Empty" interrupt.
1292
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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