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Control Registers

27.3.20 SPI Default Chip Select Register (SPIDEF)

Figure 27-55. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch]

31 16

Reserved

R-0

15 8 7 0

Reserved CSDEF

R-0 R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27-28. SPI Default Chip Select Register (SPIDEF) Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Read returns 0. Writes have no effect.

7-0 CDEF Chip select default pattern. Master-mode only.

The CSDEFx bits are output to the SPISCS pins when no transmission is being performed. It allows the

user to set a programmable chip-select pattern that deselects all of the SPI slaves.

0 SPISCSx is set to 0 when no transfer is active.

1 SPISCSx is set to 1 when no transfer is active.

1289

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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