Datasheet

SCS
ENA
CLK
SOMI
t
C2EDELAY
SCS
ENA
CLK
SOMI
1
t
SCS
CLK
SOMI
VCLK
t
T2CDELAY
SCS
CLK
SOMI
VCLK
t
C2TDELAY
Control Registers www.ti.com
Figure 27-51. Example: t
C2TDELAY
= 8 VCLK Cycles
Figure 27-52. Example: t
T2CDELAY
= 4 VCLK Cycles
Figure 27-53. Transmit-Data-Finished-to-ENA-Inactive-Timeout
Figure 27-54. Chip-Select-Active-to-ENA-Signal-Active-Timeout
1288
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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