Datasheet

t
cyc(DMM)
t
r
t
f
t
h(DMM)
t
l(DMM)
151
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.22.10 Data Modification Module (DMM)
The Data Modification Module (DMM) provides the capability to modify data in the entire 4GB address
space of the RM57Dx devices from an external peripheral, with minimal interruption of the application.
6.22.10.1 DMM Features
The DMM module has the following features:
• Acts as a bus master, enabling direct writes to the 4GB address space without CPU intervention
• Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM Trace Port (RTP) module
• Writes received data to consecutive addresses, which are specified by the DMM module (leverages
packets defined by direct data mode of the RTP module)
• Configurable port width (1-, 2-, 4-, 8-, 16-pins)
• Up to 100 Mbps terminal data rate
• Unused pins configurable as GIO pins
6.22.10.2 Timing Specifications
Table 6-61. DMMCLK Timing (see Figure 6-35)
PARAMETER MIN MAX UNIT
t
cyc(DMM)
Cycle time, DMMCLK clock period 9.09 ns
t
h(DMM)
High-pulse width ((t
cyc(DMM)
)/2) - ((t
r
+t
f
)/2) ns
t
l(DMM)
Low-pulse width ((t
cyc(DMM)
)/2) - ((t
r
+t
f
)/2) ns
Figure 6-35. DMMCLK Timing
Table 6-62. DMMDATA Timing (see Figure 6-36)
PARAMETER MIN MAX UNIT
t
ssu(DMM)
Setup time, SYNC active before clk falling edge 2 ns
t
sh(DMM)
Hold time, clk falling edge after SYNC deactive 3 ns
t
dsu(DMM)
Setup time, DATA before clk falling edge 2 ns
t
dh(DMM)
Hold time, clk falling edge after DATA hold time 3 ns