Datasheet

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27.3.16 SPI Transmit Data Register 1 (SPIDAT1)
Figure 27-47. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]
31 29 28 27 26 25 24 23 16
Reserved CSHOLD Rsvd WDEL DFSEL CSNR
R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0
15 0
TXDATA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27-24. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Read returns 0. Writes have no effect.
28 CSHOLD Chip select hold mode. The CSHOLD bit is supported in master mode only in compatibility-mode of
SPI, (it is ignored in slave mode). CSHOLD defines the behavior of the chip select line at the end of a
data transfer.
0 The chip select signal is deactivated at the end of a transfer after the T2CDELAY time has passed. If
two consecutive transfers are dedicated to the same chip select this chip select signal will be
deactivated for at least 2VCLK cycles before it is activated again.
1 The chip select signal is held active at the end of a transfer until a control field with new data and
control information is loaded into SPIDAT1. If the new chip select number equals the previous one,
the active chip select signal is extended until the end of transfer with CSHOLD cleared, or until the
chip-select number changes.
27 Reserved 0 Reads returns 0. Writes have no effect.
26 WDEL Enable the delay counter at the end of the current transaction.
Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored.
0 No delay will be inserted. However, SPISCS pins will still be de-activated for at least for 2VCLK
cycles if CSHOLD = 0.
Note: The duration for which the SPISCS pin remains deactivated depends upon the time
taken to supply a new word after completing the shift operation. If TXBUF is already full, then
the SPISCS will be deasserted for at least two VCLK cycles (if WDEL = 0).
1 After a transaction, WDELAY of the corresponding data format will be loaded into the delay counter.
No transaction will be performed until the WDELAY counter overflows. The SPISCS pins will be de-
activated for at least (WDELAY + 2) × VCLK_Period duration.
25-24 DFSEL Data word format select
0 Data word format 0 is selected
1h Data word format 1 is selected
2h Data word format 2 is selected
3h Data word format 3 is selected
23-16 CSNR 0-FFh Chip select number. CSNR defines the chip-select that will be activated during the data transfer.
Note: Writing to only the control field does not initiate any SPI transfer in master mode. This
feature can be used to set up SPICLK phase or polarity before actually starting the transfer by
only updating the DFSEL fields in the control field to select the required phase/polarity
combination.
15-0 TXDATA 0-FFFFh Transfer data.When written, these bits are copied to the shift register if it is empty. If the shift register
is not empty, then they are held in TXBUF.
SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the lower
16 bits of SPIDAT1 to 0x0000.
Write to this register ONLY when using the automatic slave chip-select feature (see Section 27.2.1.1).
A write to this register will drive the contents of CSNR[3:0] on the SPISCS[3:0] pins, if they are
configured as functional pins.
When this register is read, the contents of TXBUF, which holds the latest data written, will be
returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.
1283
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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