Datasheet

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Table 27-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions (continued)
Bit Field Value Description
9 CLKPDIS CLK pull control enable/disable. This bit enables pull control capability for the pin SPICLK pin if it is in
input mode regardless of whether it is in functional or GIO mode.
0 Pull control on the CLK pin is enabled.
1 Pull control on the CLK pin is disabled.
8 ENAPDIS ENABLE pull control enable/disable. This bit enables pull control capability for the pin SPIENA pin if it
is in input mode regardless of whether it is in functional or GIO mode.
0 Pull control on ENABLE pin is enabled.
1 Pull control on ENABLE pin is disabled.
7-0 SCSPDIS SCSx pull control enable/disable. This bit enables pull control capability for the pin SPISCSx pin if it is
in input mode regardless of whether it is in functional or GIO mode.
0 Pull control on SCSx pin is enabled.
1 Pull control on SCSx pin is disabled.
27.3.14 SPI Pin Control Register 8 (SPIPC8)
NOTE: Register bits vary by device
Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.
NOTE: Default Register Value
The default values of these register bits vary by device. See your device datasheet for
information about default pin states, which correspond to the register reset values (see the
pin-list table).
Figure 27-45. SPI Pin Control Register 8 (SPIPC8) [offset = 34h]
31 24 23 16
SOMIPSEL SIMOPSEL
R/W-x R/W-x
15 12 11 10 9 8
Reserved SOMIPSEL0 SIMOPSEL0 CLKPSEL ENAPSEL
R-0 R/W-x R/W-x R/W-x R/W-x
7 0
SCSPSEL
R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value varies by device
Table 27-22. SPI Pin Control Register 8 (SPIPC8) Field Descriptions
Bit Field Value Description
31-24 SOMIPSEL SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin.
Note: Bit 11 or bit 24 can be used to set pull-select for SPISOMI0. If a 32-bit write is
performed, bit 11 will have priority over bit 24.
0 Pull down on SOMIx pin
1 Pull up on SOMIx pin
1281
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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