Datasheet

Control Registers www.ti.com
27.3.13 SPI Pin Control Register 7 (SPIPC7)
NOTE: Register bits vary by device
Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.
NOTE: Default Register Value
The default values of these register bits vary by device. See your device datasheet for
information about default pin states, which correspond to the register reset values (see the
pin-list table).
Figure 27-44. SPI Pin Control Register 7 (SPIPC7) [offset = 30h]
31 24 23 16
SOMIDIS SIMODIS
R/W-x R/W-x
15 12 11 10 9 8
Reserved SOMIPDIS0 SIMOPDIS0 CLKPDIS ENAPDIS
R-0 R/W-x R/W-x R/W-x R/W-x
7 0
SCSPDIS
R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value varies by device
Table 27-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions
Bit Field Value Description
31-24 SOMIDIS SOMIx pull control enable/disable. This bit enables pull control capability for the SOMIx pin if it is in
input mode regardless of whether it is in functional or GIO mode.
Note: Bit 11 or bit 24 can be used to set pull-disable for SOMIO. If a 32-bit write is performed,
bit 11 will have priority over bit 24.
0 Pull control on the SPISOMIx pin is enabled.
1 Pull control on the SPISOMIx pin is disabled.
23-16 SIMODIS SIMOx pull control enable/disable. This bit enables pull control capability for the SIMOx pin if it is in
input mode regardless of whether it is in functional or GIO mode.
Note: Bit 10 or bit 16 can be used to set pull-disable for SIMO0. If a 32-bit write is performed,
bit 10 will have priority over bit 16.
0 Pull control on SPISIMOx pin is enabled.
1 Pull control on SPISIMOx pin is disabled.
15-12 Reserved 0 Read returns 0. Writes have no effect.
11 SOMIPDIS0 SPISOMI0 pull control enable/disable. This bit enables pull control capability for the pin SPISOMI0
pin if it is in input mode regardless of whether it is in functional or GIO mode.
0 Pull control on the SPISOMI0 pin is enabled.
1 Pull control on the SPISOMI0 pin is disabled.
10 SIMOPDIS0 SPISIMO0 pull control enable/disable. This bit enables pull control capability for the pin SPISIMO0
pin if it is in input mode regardless of whether it is in functional or GIO mode.
0 Pull control on the SPISIMO0 pin is enabled.
1 Pull control on the SPISIMO0 pin is disabled.
1280
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated