Datasheet

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27.3.2 SPI Global Control Register 1 (SPIGCR1)
Figure 27-33. SPI Global Control Register 1 (SPIGCR1) [offset = 04h]
31 25 24 23 17 16
Reserved SPIEN Reserved LOOPBACK
R-0 R/W-0 R-0 R/WP-0
15 9 8 7 2 1 0
Reserved POWERDOWN Reserved CLKMOD MASTER
R-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 27-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Read returns 0. Writes have no effect.
24 SPIEN SPI enable. This bit enables SPI transfers. This bit must be set to 1 after all other SPI configuration
bits have been written. When the SPIEN bit is 0 or cleared to 0, the following SPI registers get
forced to their default states:
• Both TX and RX shift registers
• The TXDATA fields of the SPI Transmit Data Register 0 (SPIDAT0) and the SPI Transmit Data
Register 1 (SPIDAT1)
• All the fields of the SPI Flag Register (SPIFLG)
• Contents of SPIBUF and the internal RXBUF registers
0 The SPI is not activated for transfers.
1 Activates SPI
23-17 Reserved 0 Reads returns 0. Writes have no effect.
16 LOOPBACK Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. If the
SPISIMO and SPISOMI pins are configured with SPI functionality, then the SPISIMO[7:0] pins
areis internally connected to the SPISOMI[7:0] pins (transmit data is looped back as receive data).
GIO mode for these pins is not supported in loopback mode. Externally, during loop-back
operation, the SPICLK pin outputs an inactive value and SPISOMI[7:0] remains in the high-
impedance state. If the SPI is initialized in slave mode or a data transfer is ongoing, errors may
result.
Note: This loopback mode can only be used in master mode. Master mode must be selected
before setting LOOPBACK. When this mode is selected, the CLKMOD bit should be set to 1,
meaning that SPICLK is internally generated.
0 Internal loop-back test mode disabled.
1 Internal loop-back test mode enabled.
15-9 Reserved 0 Reads returns 0. Writes have no effect.
8 POWERDOWN When active, the SPI state machine enters a power-down state.
0 The SPI is in active mode.
1 The SPI is in power-down mode.
7-2 Reserved 0 Reads returns 0. Writes have no effect.
1 CLKMOD Clock mode. This bit selects either an internal or external clock source. This bit also determines the
I/O direction of the SPIENA and SPISCS[3:0] pins in functional mode.
0 Clock is external.
• SPIENA is an output.
• SPISCS[3:0] are inputs.
1 Clock is internally-generated.
• SPIENA is an output.
• SPISCS[3:0] are outputs.
1263
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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