Datasheet

Control Registers www.ti.com
Table 27-8. SPI Registers (continued)
Offset Acronym Register Description Section
124h PAR_ECC_STAT Parity/ECC Status Register Section 27.3.38
128h UERRADDR1 Uncorrectable Parity or Double Bit ECC Error Section 27.3.39
Address Register - RXRAM
12Ch UERRADDR0 Uncorrectable Parity or Double Bit ECC Error Section 27.3.40
Address Register - TXRAM
130h RXOVRN_BUF_ADDR RXRAM Overrun Buffer Address Register Section 27.3.41
134h IOLPBKTSTCR I/O Loopback Test Control Register Section 27.3.42
138h EXTENDED_PRESCALE1 SPI Extended Prescale Register 1 Section 27.3.43
13Ch EXTENDED_PRESCALE2 SPI Extended Prescale Register 2 Section 27.3.44
140h ECCDIAG_CTRL ECC Diagnostic Control Register Section 27.3.45
144h ECCDIAG_STAT ECC Diagnostic Status Register Section 27.3.46
148h SBERRADDR1 Single Bit Error Address Register - RXRAM Section 27.3.47
152h SBERRADDR0 Single Bit Error Address Register - TXRAM Section 27.3.48
27.3.1 SPI Global Control Register 0 (SPIGCR0)
Figure 27-32. SPI Global Control Register 0 (SPIGCR0) [offset = 00h]
31 16
Reserved
R-0
15 1 0
Reserved nRESET
R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 27-9. SPI Global Control Register 0 (SPIGCR0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Read returns 0. Writes have no effect.
0 nRESET This is the local reset control for the module. This bit needs to be set to 1 before any operation on SPI /
MibSPI can be done. Only after setting this bit to 1, the Auto Initialization of Multi-buffer RAM starts.
Clearing this bit to 0 will result in all of the control and status register values to return to their default
values..
0 SPI is in the reset state.
1 SPI is out of the reset state.
1262
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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