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Control Registers
27.3 Control Registers
This section describes the SPI control, data, and pin registers. The registers support 8-bit, 16-bit and 32-
bit writes. The offset is relative to the associated base address of this module in a system. The base
address for the control registers is FFF7 F400h for MibSPI1, FFF7 F600h for MibSPI2, FFF7 F800h for
MibSPI3, FFF7 FA00h for MibSPI4, and FFF7 FC00h for MibSPI5.
NOTE: TI highly recommends that write values corresponding to the reserved locations of registers
be maintained as 0 consistently. This allows future enhancements to use these reserved bits
as control bits without affecting the functionality of the module with any older versions of
software.
Table 27-8. SPI Registers
Offset Acronym Register Description Section
00h SPIGCR0 SPI Global Control Register 0 Section 27.3.1
04h SPIGCR1 SPI Global Control Register 1 Section 27.3.2
08h SPIINT0 SPI Interrupt Register Section 27.3.3
0Ch SPILVL SPI Interrupt Level Register Section 27.3.4
10h SPIFLG SPI Flag Register Section 27.3.5
14h SPIPC0 SPI Pin Control Register 0 Section 27.3.6
18h SPIPC1 SPI Pin Control Register 1 Section 27.3.7
1Ch SPIPC2 SPI Pin Control Register 2 Section 27.3.8
20h SPIPC3 SPI Pin Control Register 3 Section 27.3.9
24h SPIPC4 SPI Pin Control Register 4 Section 27.3.10
28h SPIPC5 SPI Pin Control Register 5 Section 27.3.11
2Ch SPIPC6 SPI Pin Control Register 6 Section 27.3.12
30h SPIPC7 SPI Pin Control Register 7 Section 27.3.13
34h SPIPC8 SPI Pin Control Register 8 Section 27.3.14
38h SPIDAT0 SPI Transmit Data Register 0 Section 27.3.15
3Ch SPIDAT1 SPI Transmit Data Register 1 Section 27.3.16
40h SPIBUF SPI Receive Buffer Register Section 27.3.17
44h SPIEMU SPI Emulation Register Section 27.3.18
48h SPIDELAY SPI Delay Register Section 27.3.19
4Ch SPIDEF SPI Default Chip Select Register Section 27.3.20
50h-5Ch SPIFMT SPI Data Format Registers Section 27.3.21
60h INTVECT0 Interrupt Vector 0 Section 27.3.22
64h INTVECT1 Interrupt Vector 1 Section 27.3.23
6Ch SPIPMCTRL Parallel/Modulo Mode Control Register Section 27.3.24
70h MIBSPIE Multi-buffer Mode Enable Register Section 27.3.25
74h TGITENST TG Interrupt Enable Set Register Section 27.3.26
78h TGITENCR TG Interrupt Enable Clear Register Section 27.3.27
7Ch TGITLVST Transfer Group Interrupt Level Set Register Section 27.3.28
80h TGITLVCR Transfer Group Interrupt Level Clear Register Section 27.3.29
84h TGINTFLG Transfer Group Interrupt Flag Register Section 27.3.30
90h TICKCNT Tick Count Register Section 27.3.31
94h LTGPEND Last TG End Pointer Section 27.3.32
98h-D4h TGxCTRL TGx Control Registers Section 27.3.33
D8h-F4h DMAxCTRL DMA Channel Control Registers Section 27.3.34
F8h-114h ICOUNT DMAxCOUNT Registers Section 27.3.35
118h DMACNTLEN DMA Large Count Register Section 27.3.36
120h PAR_ECC_CTRL Parity/ECC Control Register Section 27.3.37
1261
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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