Datasheet

Basic Operation

www.ti.com

27.2.11.2 MibSPI Mode Configuration

The following list details the configuration steps that software should perform prior to the transmission or

reception of data in MIBSPI mode. As long as SPIENA is held low the entire time that the SPI is being

configured, the order in which the registers are programmed is not important.

• Enable SPI by setting RESET bit.

• Set MSPIENA to 1 to get access to multi-buffer mode registers.

• Configure the SIMO, SOMI, CLK and optional CSx, ENA pins for SPI functionality by setting the

corresponding bit in SPIPC0 register.

• Configure the module to function as Master or Slave using CLKMOD and MASTER bits.

• Configure the required SPI data format using SPIFMTx register.

• If the module is selected to function as Master, the delay parameters can be configured using

SPIDELAY register.

• Check for BUFINITACTIVE bit to be active before configuring MIBSPI RAM. (From Device Power On it

take Number of Buffers × Peripheral clock period to initialize complete RAM.)

• Enable the Transfer Group interrupts using TGITENST register if required.

• Enable error interrupts using SPIINT0 register if required.

• Set SPIENA to 1 after the SPI is configured.

• The Trigger Source, Trigger Event, Transfer Group start address for the corresponding Transfer

groups can be configured using the corresponding TGxCTRL register.

• Configure LPEND to specify the end address of the last TG.

• Similar to SPIDAT1 register 16 Bit Control fields in every TXRAM buffer in the TG has to be

configured.

• Configure one of the eight BUFMODE available for each buffer.

• Fill the data to be transmitted in TXDATA field in TXRAM buffers.

• Configure TGENA bit to enable the required Transfer groups. (In case of Trigger event always setting

TGENA will trigger the transfer group).

• At the occurrence of the correct trigger event the Transfer group will be triggered and data gets

transmitted and received one after the other with out any CPU intervention.

• User can poll Transfer-group interrupt flag or wait for a transfer-completed interrupt to read and write

new data to the buffers.

1260

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

Submit Documentation Feedback