Datasheet

CTRL & Tx STAT & Rx

Seq.

SPISCS [3:0]

TG 0 Trigger

TG 14 Trigger

CS decoder

RXBUF

SPISOMI SPISIMOSPICLK SPIENA

Buffer RAM

Shift Register Parity

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Basic Operation

Figure 27-30. Multi-buffer in Slave Mode

When the SPIDAT1 register is updated, the enable signal is released, and the transaction could begin. If

the enable signal is not used, the master should wait for 6 VBUSPCLK cycles before sending the clock to

begin the transaction. This time allows the MibSPI to update the SPIDAT1 register.

Once the transaction is finished, the MibSPI writes back the content of the shift-register into the Rx buffer

and updates the status field.

NOTE: If all the Transfer Groups are not needed, the number of SPISCS that need to be in

functional mode could be reduced to 3, 2 or 1 by using the SPIPC0 register. In these cases,

the maximum number of Transfer Group accessible are respectively 7, 3 and 1. The pins that

are set in GPIO mode are not decoded.

MibSPI in 3-pin and 4pin (with SPIENA) configuration, supports multi-buffer mode too. However it is

restricted to have just one transfer group. Only the transfer group0 (TG0) can be used in this mode. Entire

multi-buffer RAM can be configured for TG0 alone. “PSTART” field in TG1CTRL register should be used

to configure the size of the multi-buffer (end of the buffers) for TG0.

NOTE: The maximum input frequency on the SPICLK pin when in slave mode is VBUSPCLK

frequency /2. If the Slave is configured in either 3-pin or 4-pin (without SPIENA) modes, then,

between end of last SPICLK and the start of SPICLK for next buffer, there should be at least

6 VCLK cycles of delay.

1253

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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