Datasheet
Shift register
1514 1312 11 10 9 8 7 6 5 4 3 2 1 0
SOMI[0]
SIMO[7]
SIMO[6]
SIMO[5]
SIMO[4]
SIMO[3]
SIMO[2]
SIMO[1]
SIMO[0]
SOMI[1]
SOMI[2]
SOMI[3]
SOMI[4]
SOMI[5]
SOMI[6]
SOMI[7]
Conceptual block diagram
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Basic Operation
27.2.6.6.6 8-Data Line Mode (MSB First, Phase 0, Polarity 0)
In 8-data line mode (master mode) the shift register bits 15, 13, 11, 9, 7, 5 and 3 will be connected to the
pins SIMO[7], SIMO[6], SIMO[5], SIMO[4], SIMO[3], SIMO[2], SIMO[1], and SIMO[0], and the shift-register
bits 14, 12, 10, 8, 6, 4, and 0 will be connected to the pins SOMI[7], SOMI[6], SOMI[5], SOMI[4], SOMI[3],
SOMI[2], SOMI[1], and SOMI[0] (or vice versa in slave mode).
After writing to SPIDAT0/SPIDAT1, the bits 15, 13, 11, 9, 7, 5, 3, and 1 will be output on SIMO[7],
SIMO[6], SIMO[5], SIMO[4], SIMO[3], SIMO[2], SIMO[1], and SIMO[0], on the rising edge of SPICLK. On
the falling clock edge of the SPICLK, the received data on SOMI[8], SOMI[7], SOMI[6],SOMI[5], SOMI[4],
SOMI[3], SOMI[2], SOMI[1], and SOMI[0] will be latched to the shift register bits 14, 12, 10, 8, 6, 4, 2, and
0.
The subsequent rising edge of SPICLK will shift the data in the shift register by one bit to the left. After two
SPICLK cycles, when the full data word is transferred the shift register (16 bits) is copied to the receive
buffer, and the RXINT flag will be set. Figure 27-28 shows the clock/data diagram of the 8-data line mode.
Figure 27-29 shows the pin timings for 8-data line mode.
Figure 27-28. Eight-data Line Mode (Phase 0, Polarity 0)
NOTE: Parity Support
Using the parity support in parallel mode may seriously affect throughput. For an eight-line
mode to transfer 16 bits of data, only two SPICLK pulses are enough. If parity is enabled,
one extra SPICLK pulse will be used to transfer and receive the parity bit. Parity will be
transmitted and received on the 0th line regardless of 1/2/4/8-line modes. During the parity
bit transfer, other data bits are not valid.
1251
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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