Datasheet

15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
15
14
13 12 11 10
9 8
7 6
5
4 3 2 1 0
VCLK
SPICLK
SIMO[1]
SIMO[0]
SOMI[1]
SOMI[0]
Shift register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIMO[1]
SIMO[0]
SOMI[0]
SOMI[1]
Conceptual Block Diagram
www.ti.com Basic Operation
27.2.6.6.4 2-Data Line Mode (MSB First, Phase 0, Polarity 0)
In 2-data line mode (master mode) the shift register bits 15 and 7 will be connected to the pins SIMO[1]
and SIMO[0], and the shift register bits 8 and 0 will be connected to the pins SOMI[1] and SOMI[0] or vice
versa in slave mode. After writing to the SPIDAT0/SPIDAT1 register, the bits 15 and 7 will be output on
SIMO[1] and SIMO[0] on the rising edge if SPICLK. With the falling clock edge of the SPICLK, the
received data on SOMI[1] and SOMI[0] will be latched to the shift register bits 8 and 0. The subsequent
rising edge of SPICLK will shift the data in the shift register by 1 bit to the left. ( SIMO[1] will shift the data
out from bit 15 to 8, SIMO[0] will shift the data out from bit 7 to 0). After eight SPICLK cycles, when the full
data word is transferred, the shift register (16 bits) is copied to the receive buffer, and the RXINT flag will
be set. Figure 27-24 shows the clock /data diagram of the 2-data line mode. Figure 27-25 shows the
timing of a two-pin parallel transfer.
Figure 27-24. 2-data Line Mode (Phase 0, Polarity 0)
Figure 27-25. Two-Pin Parallel Mode Timing Diagram (Phase 0, Polarity 0)
1249
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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