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27.2.6.6.3 Parallel Mode Pin Mapping, MSB-First, LSB-First
Table 27-6 and Table 27-7 describe the SIMO and SOMI pin mapping when SPI is used in parallel mode
(1, 2, 4, 8) pin mode, LSB first.
Table 27-6. Pin Mapping for SIMO Pin with LSB First
Parallel Mode Shift Register Bit SIMO[7:0]
1 0 0
2 8 1
0 0
4 12 3
8 2
4 1
0 0
8 14 7
12 6
10 5
8 4
6 3
4 2
2 1
0 0
Table 27-7. Pin Mapping for SOMI Pin with LSB First
Parallel Mode Shift Register Bit SOMI[7:0]
1 15 0
2 7 0
15 1
4 3 0
7 1
11 2
15 3
8 1 0
3 1
5 2
7 3
9 4
11 5
13 6
15 7
1248
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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