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Basic Operation

27.2.6.6.2 Parallel Mode Pin Mapping, MSB First

Table 27-4 and Table 27-5 describe the SOMI and SIMO pin mapping when the SPI is used in parallel

mode (1, 2, 4, 8) pin mode, MSB first.

NOTE: MSB-first or LSB-first can be configured using the SHIFTDIRx bit of the SPIFMTx registers.

Table 27-4. Pin Mapping for SIMO Pin with MSB First

Parallel Mode Shift Register Bit SIMO[7:0]

1 15 0

2 15 1

7 0

4 15 3

11 2

7 1

3 0

8 15 7

13 6

11 5

9 4

7 3

5 2

3 1

1 0

Table 27-5. Pin Mapping for SOMI Pin with MSB First

Parallel Mode Shift Register Bit SOMI[7:0]

1 0 0

2 0 0

8 1

4 0 0

4 1

8 2

12 3

8 0 0

2 1

4 2

6 3

8 4

10 5

12 6

14 7

1247

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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