Datasheet

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SIMO[7:0]
SOMI[7:0]
SPI Shift register
0
SIMO7
SIMO6
SIMO5
SIMO4
SIMO3
SIMO2
SIMO1
SIMO0
MULTIPLEXER
Parallel mode
SOMI7
SOMI6
SOMI5
SOMI4
SOMI3
SOMI2
SOMI1
SOMI0
DEMULTIPLEXER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SIMO[7:0]
SOMI[7:0]
SPI Shift register
SIMO7
SIMO6
SIMO5
SIMO4
SIMO3
SIMO2
SIMO1
SIMO0
MULTIPLEXER
Parallel mode
0
SOMI7
SOMI6
SOMI5
SOMI4
SOMI3
SOMI2
SOMI1
SOMI0
DEMULTIPLEXER
Basic Operation www.ti.com
27.2.6.6.1 Parallel Mode Block Diagram
Figure 27-22 and Figure 27-23 show the parallel connections to the SPI shift register.
Figure 27-22. Block Diagram Shift Register, MSB First
Figure 27-23. Block Diagram Shift Register, LSB First
1246
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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